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| author |   Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2018-03-30 18:44:13 +0900 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2018-04-05 15:03:49 -0700 |
| commit | 54e1f7ee1f5e8ec8b56e89fc431b3d07f84e9cbd (patch) | |
| tree | cfd091d72bade10609a129df92a885ec976816da /lib/mpi/mpi-internal.h | |
| parent | clk: uniphier: add PCIe clock control support (diff) | |
| download | wireguard-linux-54e1f7ee1f5e8ec8b56e89fc431b3d07f84e9cbd.tar.xz wireguard-linux-54e1f7ee1f5e8ec8b56e89fc431b3d07f84e9cbd.zip | |
clk: uniphier: add SATA clock control support
Add clock control for SATA controller on UniPhier SoCs. This adds
support for PXs2, LD20 and PXs3.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'lib/mpi/mpi-internal.h')
0 files changed, 0 insertions, 0 deletions