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| author |   Alex Helms <alexander.helms.jy@renesas.com> | 2022-09-12 11:36:12 -0700 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-09-30 17:34:20 -0700 |
| commit | 09d1855656dad04127aee195baf2eedae029175d (patch) | |
| tree | e3af56557df45f9fc76ac97a56cde964c2fdb3b4 /lib/overflow_kunit.c | |
| parent | Linux 6.0-rc1 (diff) | |
| download | wireguard-linux-09d1855656dad04127aee195baf2eedae029175d.tar.xz wireguard-linux-09d1855656dad04127aee195baf2eedae029175d.zip | |
dt-bindings: Renesas versaclock7 device tree bindings
Renesas Versaclock7 is a family of configurable clock generator ICs
with fractional and integer dividers. This driver has basic support
for the RC21008A device, a clock synthesizer with a crystal input and
8 outputs. The supports changing the FOD and IOD rates, and each
output can be gated.
Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220912183613.22213-2-alexander.helms.jy@renesas.com
Tested-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
[sboyd@kernel.org: Rename nodes in example to generic names]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'lib/overflow_kunit.c')
0 files changed, 0 insertions, 0 deletions