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| author |   Kishon Vijay Abraham I <kishon@ti.com> | 2020-07-22 16:33:08 +0530 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-07-27 15:46:16 +0100 |
| commit | c4c10c0125a705c606cb0cc85e18f13b490d026f (patch) | |
| tree | 409b8838f67b6233f3b0a91ac6a3906fcdda1f76 /lib/test_list_sort.c | |
| parent | PCI: cadence: Add support to start link and verify link status (diff) | |
| download | wireguard-linux-c4c10c0125a705c606cb0cc85e18f13b490d026f.tar.xz wireguard-linux-c4c10c0125a705c606cb0cc85e18f13b490d026f.zip | |
PCI: cadence: Allow pci_host_bridge to have custom pci_ops
Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.
Link: https://lore.kernel.org/r/20200722110317.4744-7-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'lib/test_list_sort.c')
0 files changed, 0 insertions, 0 deletions