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| author |   Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2018-12-14 09:37:24 +0000 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2019-01-22 15:42:27 +0100 |
| commit | 77223211f44db5b35541f4cc1fe48cdee21a85b2 (patch) | |
| tree | 9c2bcc15b3b065d96fe598db065ad1b444aa0590 /mm/debug.c | |
| parent | arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core (diff) | |
| download | wireguard-linux-77223211f44db5b35541f4cc1fe48cdee21a85b2.tar.xz wireguard-linux-77223211f44db5b35541f4cc1fe48cdee21a85b2.zip | |
arm64: dts: renesas: r8a774c0: Add SDHI nodes
Add SDHI nodes to the DT of the r8a774c0 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'mm/debug.c')
0 files changed, 0 insertions, 0 deletions