diff options
| author | 2016-02-17 10:37:36 +0100 | |
|---|---|---|
| committer | 2016-02-17 10:37:36 +0100 | |
| commit | 9109dc97b0155e500cdf3bcd91507bc24defefc1 (patch) | |
| tree | 5d721cbfeb3576dc6969093ab04f17666737b6a4 /mm/pgtable-generic.c | |
| parent | perf/x86: Move perf_event.h to its new home (diff) | |
| parent | perf/core: Plug potential memory leak in CPU_UP_PREPARE (diff) | |
| download | wireguard-linux-9109dc97b0155e500cdf3bcd91507bc24defefc1.tar.xz wireguard-linux-9109dc97b0155e500cdf3bcd91507bc24defefc1.zip | |
Merge branch 'perf/urgent' into perf/core, to queue up dependent patch
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | mm/pgtable-generic.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/mm/pgtable-generic.c b/mm/pgtable-generic.c index 9d4767698a1c..06a005b979a7 100644 --- a/mm/pgtable-generic.c +++ b/mm/pgtable-generic.c @@ -90,9 +90,9 @@ pte_t ptep_clear_flush(struct vm_area_struct *vma, unsigned long address, * ARCHes with special requirements for evicting THP backing TLB entries can * implement this. Otherwise also, it can help optimize normal TLB flush in * THP regime. stock flush_tlb_range() typically has optimization to nuke the - * entire TLB TLB if flush span is greater than a threshhold, which will + * entire TLB if flush span is greater than a threshold, which will * likely be true for a single huge page. Thus a single thp flush will - * invalidate the entire TLB which is not desitable. + * invalidate the entire TLB which is not desirable. * e.g. see arch/arc: flush_pmd_tlb_range */ #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) @@ -195,7 +195,9 @@ pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address, VM_BUG_ON(address & ~HPAGE_PMD_MASK); VM_BUG_ON(pmd_trans_huge(*pmdp)); pmd = pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); - flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE); + + /* collapse entails shooting down ptes not pmd */ + flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE); return pmd; } #endif |
