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| author |   Horatiu Vultur <horatiu.vultur@microchip.com> | 2020-06-23 11:05:40 +0200 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2020-06-23 14:38:05 -0700 |
| commit | 2464bc7c2897b7549146a743045089d3aea7b85b (patch) | |
| tree | b6aa045cdd1f7c5fd325ba1d054330040fe96f90 /net/bridge/br_mrp.c | |
| parent | GUE: Fix a typo (diff) | |
| download | wireguard-linux-2464bc7c2897b7549146a743045089d3aea7b85b.tar.xz wireguard-linux-2464bc7c2897b7549146a743045089d3aea7b85b.zip | |
bridge: uapi: mrp: Fix MRP_PORT_ROLE
Currently the MRP_PORT_ROLE_NONE has the value 0x2 but this is in conflict
with the IEC 62439-2 standard. The standard defines the following port
roles: primary (0x0), secondary(0x1), interconnect(0x2).
Therefore remove the port role none.
Fixes: 4714d13791f831 ("bridge: uapi: mrp: Add mrp attributes.")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions