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| author |   Shahar Shitrit <shshitrit@nvidia.com> | 2025-02-13 11:46:40 +0200 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2025-02-17 16:27:38 -0800 |
| commit | 633f16d7e07c129a36b882c05379e01ce5bdb542 (patch) | |
| tree | 2ab74ce381433c4d2d9292a8a5431f95afe7f2b5 /net/core/page_pool_user.c | |
| parent | net/mlx5: Prefix temperature event bitmap with '0x' for clarity (diff) | |
| download | wireguard-linux-633f16d7e07c129a36b882c05379e01ce5bdb542.tar.xz wireguard-linux-633f16d7e07c129a36b882c05379e01ce5bdb542.zip | |
net/mlx5: Modify LSB bitmask in temperature event to include only the first bit
In the sensor_count field of the MTEWE register, bits 1-62 are
supported only for unmanaged switches, not for NICs, and bit 63
is reserved for internal use.
To prevent confusing output that may include set bits that are
not relevant to NIC sensors, we update the bitmask to retain only
the first bit, which corresponds to the sensor ASIC.
Signed-off-by: Shahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Link: https://patch.msgid.link/20250213094641.226501-4-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'net/core/page_pool_user.c')
0 files changed, 0 insertions, 0 deletions