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| author |   Thippeswamy Havalige <thippeswamy.havalige@amd.com> | 2025-02-28 15:03:50 +0530 |
|---|---|---|
| committer |   Krzysztof Wilczyński <kwilczynski@kernel.org> | 2025-03-03 09:27:39 +0000 |
| commit | c96c936a0e5ad9c3f0d5b98f9028d631e5af1895 (patch) | |
| tree | ef87e4c1872d283b6245f4a2ef93e45a0fc91479 /net/lapb/lapb_timer.c | |
| parent | dt-bindings: PCI: dwc: Add AMD Versal2 MDB SLCR support (diff) | |
| download | wireguard-linux-c96c936a0e5ad9c3f0d5b98f9028d631e5af1895.tar.xz wireguard-linux-c96c936a0e5ad9c3f0d5b98f9028d631e5af1895.zip | |
dt-bindings: PCI: amd-mdb: Add AMD Versal2 MDB PCIe Root Port Bridge
Add AMD Versal2 MDB (Multimedia DMA Bridge) PCIe Root Port Bridge.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20250228093351.923615-3-thippeswamy.havalige@amd.com
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions