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author | 2015-04-27 20:36:31 +0900 | |
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committer | 2015-04-29 14:11:34 +0200 | |
commit | b57c93be79e4061b8878315df2f6a239ad967d50 (patch) | |
tree | 340c7c4030cef01c753bc3c881f9547782bcb114 /net/switchdev/switchdev.c | |
parent | clk: exynos5433: Fix CLK_PCLK_MONOTONIC_CNT clk register assignment (diff) | |
download | wireguard-linux-b57c93be79e4061b8878315df2f6a239ad967d50.tar.xz wireguard-linux-b57c93be79e4061b8878315df2f6a239ad967d50.zip |
clk: exynos5433: Fix wrong parent clock of sclk_apollo clock
This patch fixes the wrong parent clock of sclk_apollo clock
from 'div_apollo_pll' to 'div_apollo2'.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'net/switchdev/switchdev.c')
0 files changed, 0 insertions, 0 deletions