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| author |   Vlad Zolotarov <vlad@scalemp.com> | 2012-02-05 15:24:39 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2012-02-05 22:42:00 -0500 |
| commit | 94bf91baf3a16ec274de3cd913be3033c029f853 (patch) | |
| tree | 228947bbd33977940a8262512072528a64cdfa30 /net/tipc | |
| parent | bnx2: Add support for ethtool --show-channels|--set-channels (diff) | |
| download | wireguard-linux-94bf91baf3a16ec274de3cd913be3033c029f853.tar.xz wireguard-linux-94bf91baf3a16ec274de3cd913be3033c029f853.zip | |
bnx2: Add missing memory barrier in bnx2_start_xmit()
Sync DMA descriptor before hitting the TX mailbox for weak memory model
CPUs.
There has been discussions several years ago about this. Some believe
that writel() should guarantee ordering. Others want explicit barriers
if necessary. Today writel() does not have the ordering guarantee and
many other drivers use explicit barriers.
Signed-off-by: Vlad Zolotarov <vlad@scalemp.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/tipc')
0 files changed, 0 insertions, 0 deletions