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| author | 2025-09-16 10:21:37 +1000 | |
|---|---|---|
| committer | 2025-09-16 10:21:38 +1000 | |
| commit | 8299ee7ff7d545ad8cb5ebd969642414ba9df850 (patch) | |
| tree | 11e14b028734aa958ba9cda5d8d31ad73f638ac4 /rust/kernel/alloc/allocator_test.rs | |
| parent | Merge tag 'v6.17-rc6' into drm-next (diff) | |
| parent | drm/msm/registers: Sync GPU registers from mesa (diff) | |
| download | wireguard-linux-8299ee7ff7d545ad8cb5ebd969642414ba9df850.tar.xz wireguard-linux-8299ee7ff7d545ad8cb5ebd969642414ba9df850.zip | |
Merge tag 'drm-msm-next-2025-09-12' of https://gitlab.freedesktop.org/drm/msm into drm-next
Changes for v6.18
GPU and Core:
- in DT bindings describe clocks per GPU type
- GMU bandwidth voting for x1-85
- a663 speedbins
- a623 speedbins
- cleanup some remaining no-iommu leftovers after VM_BIND conversion
- fix GEM obj 32b size truncation
- add missing VM_BIND param validation
- various fixes
- IFPC for x1-85 and a750
- register xml and gen_header.py sync from mesa
Display:
- add missing bindings for display on SC8180X
- added DisplayPort MST bindings
- conversion from round_rate() to determine_rate()
- DSI PHY fixes, correcting programming glitches
- misc small fixes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://lore.kernel.org/r/CACSVV01FgXN+fD6U1Hi6Tj4WCf=V-+NO8BXi+80iS4qOZwpaGg@mail.gmail.com
Diffstat (limited to 'rust/kernel/alloc/allocator_test.rs')
0 files changed, 0 insertions, 0 deletions
