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| author |   Michal Simek <michal.simek@xilinx.com> | 2017-07-05 14:50:44 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-07-20 14:06:35 +0200 |
| commit | 26db4d8bc7cbcf95d2a60366e36c839ab3b5d6d9 (patch) | |
| tree | 8e02d5930fed13c9e9caa8a7c02dfb74aefb6913 /scripts/gcc-plugins/gcc-generate-rtl-pass.h | |
| parent | arm64: dts: xilinx: fix PCI bus dtc warnings (diff) | |
| download | wireguard-linux-26db4d8bc7cbcf95d2a60366e36c839ab3b5d6d9.tar.xz wireguard-linux-26db4d8bc7cbcf95d2a60366e36c839ab3b5d6d9.zip | |
arm64: zynqmp: Remove leading 0s from mtd table for spi flashes
Warnings:
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'scripts/gcc-plugins/gcc-generate-rtl-pass.h')
0 files changed, 0 insertions, 0 deletions