diff options
| author |   Michal Simek <michal.simek@xilinx.com> | 2017-07-05 14:51:42 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-08-21 14:07:22 +0200 |
| commit | 63301178e9a950bf3e8105926c750794d779bb29 (patch) | |
| tree | f3d3c4d5fdbfcb5d81ee0e7aa76346a59c0cd761 /scripts/gcc-plugins/gcc-generate-rtl-pass.h | |
| parent | arm64: zynqmp: Remove leading 0s from mtd table for spi flashes (diff) | |
| download | wireguard-linux-63301178e9a950bf3e8105926c750794d779bb29.tar.xz wireguard-linux-63301178e9a950bf3e8105926c750794d779bb29.zip | |
arm64: zynqmp: Move nodes which have no reg property out of bus
Nodes without reg properties shouldn't be placed in amba node.
Move them out.
Warnings:
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (simple_bus_reg):
Node /amba/misc_clk missing or empty reg/ranges property
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (simple_bus_reg):
Node /amba/i2c_clk missing or empty reg/ranges property
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (simple_bus_reg):
Node /amba/sata_clk missing or empty reg/ranges property
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (simple_bus_reg):
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'scripts/gcc-plugins/gcc-generate-rtl-pass.h')
0 files changed, 0 insertions, 0 deletions