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| author |   Zenghui Yu <yuzenghui@huawei.com> | 2024-03-27 22:23:05 +0800 |
|---|---|---|
| committer |   Thomas Gleixner <tglx@linutronix.de> | 2024-04-09 11:03:15 +0200 |
| commit | ff3669a71afa06208de58d6bea1cc49d5e3fcbd1 (patch) | |
| tree | 74f85647e9ab373e218a445384fadb68a00ef979 /scripts/gdb/linux/interrupts.py | |
| parent | irqchip/riscv-aplic: Fix spelling mistake "forwared" -> "forwarded" (diff) | |
| download | wireguard-linux-ff3669a71afa06208de58d6bea1cc49d5e3fcbd1.tar.xz wireguard-linux-ff3669a71afa06208de58d6bea1cc49d5e3fcbd1.zip | |
irqchip/alpine-msi: Fix off-by-one in allocation error path
When alpine_msix_gic_domain_alloc() fails, there is an off-by-one in the
number of interrupts to be freed.
Fix it by passing the number of successfully allocated interrupts, instead
of the relative index of the last allocated one.
Fixes: 3841245e8498 ("irqchip/alpine-msi: Fix freeing of interrupts on allocation error path")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240327142305.1048-1-yuzenghui@huawei.com
Diffstat (limited to 'scripts/gdb/linux/interrupts.py')
0 files changed, 0 insertions, 0 deletions