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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2025-04-17 06:43:02 +0100 |
|---|---|---|
| committer |   Marc Kleine-Budde <mkl@pengutronix.de> | 2025-05-21 14:31:23 +0200 |
| commit | 466c8ef7b66bf4595537333e96c7334e1ceb454a (patch) | |
| tree | a2daf1c104cfcfe21b82fde1820ced246aa831a7 /scripts/gdb/linux/modules.py | |
| parent | octeontx2-pf: Add tracepoint for NIX_PARSE_S (diff) | |
| download | wireguard-linux-466c8ef7b66bf4595537333e96c7334e1ceb454a.tar.xz wireguard-linux-466c8ef7b66bf4595537333e96c7334e1ceb454a.zip | |
dt-bindings: can: renesas,rcar-canfd: Simplify the conditional schema
RZ/G3E SoC has 20 interrupts, 2 resets and 6 channels that need more
branching with conditional schema. Simplify the conditional schema with
if statements rather than the complex if-else statements to prepare for
supporting RZ/G3E SoC.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20250417054320.14100-2-biju.das.jz@bp.renesas.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions