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| author |   Zhi Wang <zhi.a.wang@intel.com> | 2017-12-29 02:50:08 +0800 |
|---|---|---|
| committer |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-01-04 14:23:28 +0800 |
| commit | 121d760d0788f95619049c63449d977065cab69d (patch) | |
| tree | 386ce4f5f14d94013416994fe660ef26d20abdb3 /scripts/gdb/linux/tasks.py | |
| parent | drm/i915/gvt: Fix pipe A enable as default for vgpu (diff) | |
| download | wireguard-linux-121d760d0788f95619049c63449d977065cab69d.tar.xz wireguard-linux-121d760d0788f95619049c63449d977065cab69d.zip | |
drm/i915/gvt: Clear the shadow page table entry after post-sync
A shadow page table entry needs to be cleared after being set as
post-sync. This patch fixes the recent error reported in Win7-32 test.
Fixes: 2707e4446688 ("drm/i915/gvt: vGPU graphics memory virtualization")
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
CC: Stable <stable@vger.kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions