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| author |   Palmer Dabbelt <palmer@sifive.com> | 2017-11-28 14:06:31 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2017-11-28 14:06:31 -0800 |
| commit | bf730552734372e45b10fe056726de1950fdfdde (patch) | |
| tree | bb7872d1a46c98aa3fe9cd7c27f24bde1a4d1f90 /scripts/gdb/linux/tasks.py | |
| parent | RISC-V: `sfence.vma` orderes the instruction cache (diff) | |
| download | wireguard-linux-bf730552734372e45b10fe056726de1950fdfdde.tar.xz wireguard-linux-bf730552734372e45b10fe056726de1950fdfdde.zip | |
RISC-V: remove spin_unlock_wait()
This was removed from the other architectures in commit
952111d7db02 ("arch: Remove spin_unlock_wait() arch-specific
definitions"). That landed between when we got upstream and when our
patches were reviewed, so this is a followup patch.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions