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| author |   Palmer Dabbelt <palmer@sifive.com> | 2017-11-28 14:06:17 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2017-11-28 14:06:17 -0800 |
| commit | c901e45a999a1935d7adf653e1cf12dfbcd737aa (patch) | |
| tree | 2d30d6656ef0d3fd57f78045830b9c21ae69a5ae /scripts/gdb/linux/tasks.py | |
| parent | RISC-V: Add READ_ONCE in arch_spin_is_locked() (diff) | |
| download | wireguard-linux-c901e45a999a1935d7adf653e1cf12dfbcd737aa.tar.xz wireguard-linux-c901e45a999a1935d7adf653e1cf12dfbcd737aa.zip | |
RISC-V: `sfence.vma` orderes the instruction cache
This is just a comment change, but it's one that bit me on the mailing
list. It turns out that issuing a `sfence.vma` enforces instruction
cache ordering in addition to TLB ordering. This isn't explicitly
called out in the ISA manual, but Andrew will be making that more clear
in a future revision.
CC: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions