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| author |   Andre Przywara <andre.przywara@arm.com> | 2025-03-07 00:26:25 +0000 |
|---|---|---|
| committer |   Chen-Yu Tsai <wens@csie.org> | 2025-03-12 11:58:11 +0800 |
| commit | 00bc60ea24a7b31da97a3b8a833711491c285ae4 (patch) | |
| tree | ab8e62a0a6d0c16106801c3500d82c7e5979f36a /scripts/gdb/linux/utils.py | |
| parent | clk: sunxi-ng: a523: add USB mod clocks (diff) | |
| download | wireguard-linux-00bc60ea24a7b31da97a3b8a833711491c285ae4.tar.xz wireguard-linux-00bc60ea24a7b31da97a3b8a833711491c285ae4.zip | |
clk: sunxi-ng: a523: remaining mod clocks
Add the remaining mod clocks, driving various parts of the SoC: the "LEDC"
LED controller, the "CSI" camera interface, the "ISP" image processor,
the DSP clock, and the "fanout" clocks, which allow to put clock signals
on external pins.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307002628.10684-12-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions