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| author |   Dharma Balasubiramani <dharma.b@microchip.com> | 2024-12-06 12:59:51 -0700 |
|---|---|---|
| committer |   Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2024-12-17 10:10:20 +0200 |
| commit | 188002bd234035199769cb1a8c7a20b51754327b (patch) | |
| tree | 38f2e481f667cccd1874645c5cfd9f1e0356af3d /scripts/gdb/linux/utils.py | |
| parent | clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks (diff) | |
| download | wireguard-linux-188002bd234035199769cb1a8c7a20b51754327b.tar.xz wireguard-linux-188002bd234035199769cb1a8c7a20b51754327b.zip | |
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65
Add bindings for SAMA7D65's slow clock controller.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/b7a8a22a571f6fc2be56a25f26757f37fa8d2bb3.1733505542.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions