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| author |   Pankaj Dubey <pankaj.dubey@samsung.com> | 2014-09-29 13:17:46 +0530 |
|---|---|---|
| committer |   Sylwester Nawrocki <s.nawrocki@samsung.com> | 2014-12-02 12:28:20 +0100 |
| commit | 2e41b9fc11f2d242f39b36ceba833471629ba3d5 (patch) | |
| tree | 59a7114db7a741606aa1f74b62a85b8de832c9ec /scripts/gdb/linux/utils.py | |
| parent | clk: samsung: exynos7: add gate clock for ADC block (diff) | |
| download | wireguard-linux-2e41b9fc11f2d242f39b36ceba833471629ba3d5.tar.xz wireguard-linux-2e41b9fc11f2d242f39b36ceba833471629ba3d5.zip | |
clk: samsung: Spelling s/bwtween/between/
Fix a typo in comment section of "struct samsung_clk_provider".
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions