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| author |   Mario Limonciello <mario.limonciello@amd.com> | 2024-12-09 12:52:40 -0600 |
|---|---|---|
| committer | Mario Limonciello <mario.limonciello@amd.com> | 2024-12-11 10:44:53 -0600 |
| commit | 474e7218e81e7932ed18f91969b72169005ff038 (patch) | |
| tree | 8eaebd1b8667b5621afa8045d62d5860a8a6f7c5 /scripts/gdb/linux/utils.py | |
| parent | cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros (diff) | |
| download | wireguard-linux-474e7218e81e7932ed18f91969b72169005ff038.tar.xz wireguard-linux-474e7218e81e7932ed18f91969b72169005ff038.zip | |
cpufreq/amd-pstate: Only update the cached value in msr_set_epp() on success
If writing the MSR MSR_AMD_CPPC_REQ fails then the cached value in the
amd_cpudata structure should not be updated.
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
Link: https://lore.kernel.org/r/20241209185248.16301-8-mario.limonciello@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions