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| author |   Shobhit Kumar <shobhit.kumar@intel.com> | 2015-02-05 17:08:45 +0530 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2015-02-09 20:21:08 +0200 |
| commit | 4ba7d93afee0a2ddef7598f460927d39f33fe98b (patch) | |
| tree | 06063a0ddbbf58551f5fe18c7b68332ba68ee1e5 /scripts/gdb/linux/utils.py | |
| parent | drm/i915: Insert a command barrier on BLT/BSD cache flushes (diff) | |
| download | wireguard-linux-4ba7d93afee0a2ddef7598f460927d39f33fe98b.tar.xz wireguard-linux-4ba7d93afee0a2ddef7598f460927d39f33fe98b.zip | |
drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL
LP_OUTPUT_HOLD is only in MIPI_PORT_CTRL(PORT_A) even for PORT_C in case
of dual link. In the dual link implementation, the bit is correctly set
or unset for hardcoded PORT_A, but for bit update the register base value
is read by using MIPI_PORT_CTRL(port) in a loop. The second iteration will
read base value from PORT_C and program for PORT_A. Mostly in case of dual
link all other bit values should be same, but logically we should read from
PORT_A. So hardcode to read initial value from PORT_A as well.
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions