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| author |   Sam Shih <sam.shih@mediatek.com> | 2022-01-05 18:04:55 +0800 |
|---|---|---|
| committer |   Wim Van Sebroeck <wim@linux-watchdog.org> | 2022-05-08 10:34:04 +0200 |
| commit | 5794dda109fc870fce48a8cdf580750b40bf9d15 (patch) | |
| tree | 628c063ebf6b775320eb3b1b63683fd27f666b67 /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: watchdog: renesas,wdt: Document RZ/V2L SoC (diff) | |
| download | wireguard-linux-5794dda109fc870fce48a8cdf580750b40bf9d15.tar.xz wireguard-linux-5794dda109fc870fce48a8cdf580750b40bf9d15.zip | |
dt-bindings: reset: mt7986: Add reset-controller header file
Add infracfg, toprgu, and ethsys reset-controller header file
for MT7986 platform.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220105100456.7126-2-sam.shih@mediatek.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions