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| author |   Sonny Rao <sonnyrao@chromium.org> | 2014-11-18 23:15:19 -0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2014-11-28 00:37:47 +0100 |
| commit | 6d288b169bdfbed28d308b077af3d9196025cd8b (patch) | |
| tree | c0351514c50f102862cc3bfc1c3fc2b2d855b378 /scripts/gdb/linux/utils.py | |
| parent | clk: rockchip: use clock ID for DMC (memory controller) on rk3288 (diff) | |
| download | wireguard-linux-6d288b169bdfbed28d308b077af3d9196025cd8b.tar.xz wireguard-linux-6d288b169bdfbed28d308b077af3d9196025cd8b.zip | |
clk: rockchip: rk3288 export i2s0_clkout for use in DT
This exposes the clock that comes out of the i2s block which generally
goes to the audio codec.
Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
[removed CLK_SET_RATE_PARENT from original patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions