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| author |   Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2024-08-26 20:31:15 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2024-12-08 17:55:26 +0200 |
| commit | 802244fae1f8f151ec2a4ba091a0cb14b32ac27f (patch) | |
| tree | 18dae6e8a6fc98d214aeddd8c3959df699a35c44 /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: clk: at91: Add clock IDs for the slow clock controller (diff) | |
| download | wireguard-linux-802244fae1f8f151ec2a4ba091a0cb14b32ac27f.tar.xz wireguard-linux-802244fae1f8f151ec2a4ba091a0cb14b32ac27f.zip | |
clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks
Use the newly introduced macros instead of raw numbers. With this the code
is a bit easier to understand.
Reviewed-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20240826173116.3628337-3-claudiu.beznea@tuxon.dev
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions