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| author |   Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2025-01-08 10:36:36 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2025-01-13 13:35:38 -0800 |
| commit | 830d8062d25581cf0beaa334486eea06834044da (patch) | |
| tree | 164f76bd2e133043b329eb4f0ef28b143d458f83 /scripts/gdb/linux/utils.py | |
| parent | clk: mediatek: mt2701-img: add missing dummy clk (diff) | |
| download | wireguard-linux-830d8062d25581cf0beaa334486eea06834044da.tar.xz wireguard-linux-830d8062d25581cf0beaa334486eea06834044da.zip | |
clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883
Ralink SoC RT3883 has already 'xtal' defined as a base clock so there is no
need to redefine it again in fixed clocks section. Hence, remove the duplicate
one from there.
Fixes: d34db686a3d7 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20250108093636.265033-1-sergio.paracuellos@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions