diff options
author | 2022-05-12 09:12:09 -0700 | |
---|---|---|
committer | 2022-05-12 09:12:09 -0700 | |
commit | 93c0651617a62a69717299f1464dda798af8bebb (patch) | |
tree | 43091139fcd158f95366c3a98bc67f5ab5f7434a /scripts/gdb/linux/utils.py | |
parent | riscv: dts: rename the node name of dma (diff) | |
parent | riscv: add memory-type errata for T-Head (diff) | |
download | wireguard-linux-93c0651617a62a69717299f1464dda798af8bebb.tar.xz wireguard-linux-93c0651617a62a69717299f1464dda798af8bebb.zip |
riscv: support for Svpbmt and D1 memory types
Adds support for Svpbmt, the "Supervisor-mode: page-based memory types"
extension, which allows pages to be marked as non-cacheable and/or I/O.
This also includes support for the Allwinner D1's page table attributes
via the alternatives framework, which differ from Svpbmt in various ways
but are necessary to make the D1 function.
* palmer/riscv-d1:
riscv: add memory-type errata for T-Head
riscv: don't use global static vars to store alternative data
riscv: remove FIXMAP_PAGE_IO and fall back to its default value
riscv: add RISC-V Svpbmt extension support
riscv: Fix accessing pfn bits in PTEs for non-32bit variants
riscv: move boot alternatives to after fill_hwcap
riscv: prevent compressed instructions in alternatives
riscv: extend concatenated alternatives-lines to the same length
riscv: implement ALTERNATIVE_2 macro
riscv: implement module alternatives
riscv: allow different stages with alternatives
riscv: integrate alternatives better into the main architecture
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions