diff options
| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-11-13 15:35:16 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-12-03 10:19:19 +0100 |
| commit | 97088b3a8e71ed87fbb25a34b222d869033d73df (patch) | |
| tree | c288cb90ccff850f0c9a533cdae7c3c735a2a473 /scripts/gdb/linux/utils.py | |
| parent | clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init() (diff) | |
| download | wireguard-linux-97088b3a8e71ed87fbb25a34b222d869033d73df.tar.xz wireguard-linux-97088b3a8e71ed87fbb25a34b222d869033d73df.zip | |
clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSI
Add SSI clocks, resets and power domains support for the SSI blocks
available on the Renesas RZ/G3S SoC.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241113133540.2005850-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions