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authorMark Brown <broonie@kernel.org>2025-02-04 22:54:23 +0000
committerMark Brown <broonie@kernel.org>2025-02-04 22:54:23 +0000
commit98fcb50a98424efb9176d075c71e5af48b6104dd (patch)
tree2169b81e3578cc291ce4eb4d0e45ba8cef98f5e3 /scripts/gdb/linux/utils.py
parentASoC: rockchip: i2s-tdm: fix shift config for SND_SOC_DAIFMT_DSP_[AB] (diff)
parentASoC: Intel: soc-acpi-intel-mtl-match: declare adr as ull (diff)
downloadwireguard-linux-98fcb50a98424efb9176d075c71e5af48b6104dd.tar.xz
wireguard-linux-98fcb50a98424efb9176d075c71e5af48b6104dd.zip
ASoC: Intel: soc-acpi-intel-tgl/mtl-match: declare adr
Merge series from Bard Liao <yung-chuan.liao@linux.intel.com>: The adr is u64.
Diffstat (limited to 'scripts/gdb/linux/utils.py')
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