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author | 2022-03-01 17:35:00 -0600 | |
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committer | 2022-03-28 20:17:55 -0500 | |
commit | a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe (patch) | |
tree | 7df099a728cfbf838017a40e844030abd66c478f /scripts/gdb/linux/utils.py | |
parent | dt-bindings: net: snps,dwmac: modify available values of PBL (diff) | |
download | wireguard-linux-a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe.tar.xz wireguard-linux-a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe.zip |
dt-bindings: media: mediatek,vcodec: Fix addressing cell sizes
'dma-ranges' in the example is written for cell sizes of 2 cells, but
the schema and example specify sizes of 1 cell. As the h/w has a bus
address of >32-bits, cell sizes of 2 is correct. Update the schema's
'#address-cells' and '#size-cells' to be 2 and adjust the example
throughout.
There's no error currently because dtc only checks 'dma-ranges' is a
correct multiple number of cells (3) and the schema checking is based on
bracketing of entries.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220301233501.2110047-1-robh@kernel.org
Diffstat (limited to 'scripts/gdb/linux/utils.py')
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