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| author |   Heiko Stuebner <heiko@sntech.de> | 2022-05-11 21:29:12 +0200 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-05-11 21:36:31 -0700 |
| commit | a8e910168bbad5c901202727470e601eb2489ec1 (patch) | |
| tree | 52b0a290b18ae5e879f8d01b013e10a2097bd717 /scripts/gdb/linux/utils.py | |
| parent | riscv: allow different stages with alternatives (diff) | |
| download | wireguard-linux-a8e910168bbad5c901202727470e601eb2489ec1.tar.xz wireguard-linux-a8e910168bbad5c901202727470e601eb2489ec1.zip | |
riscv: implement module alternatives
This allows alternatives to also be applied when loading modules
and follows the implementation of other architectures (e.g. arm64).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Link: https://lore.kernel.org/r/20220511192921.2223629-4-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions