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| author |   Michal Simek <michal.simek@xilinx.com> | 2015-01-15 14:12:46 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-01-28 15:18:32 +0100 |
| commit | ab216ac5a236756c4560ff7f07ec7e206acdf078 (patch) | |
| tree | 7abdcf4c671f340605687f245b49ad0e78c1e562 /scripts/gdb/linux/utils.py | |
| parent | ARM: zynq: DT: Fix binding for cadence WDT (diff) | |
| download | wireguard-linux-ab216ac5a236756c4560ff7f07ec7e206acdf078.tar.xz wireguard-linux-ab216ac5a236756c4560ff7f07ec7e206acdf078.zip | |
ARM: zynq: DT: Add aliases node
Add aliases node to DTs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions