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| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-12-10 19:09:30 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2024-12-10 14:49:24 -0800 |
| commit | ae6040cd7c7f8e80deefe5a49691734480f97409 (patch) | |
| tree | ed042c0e9ba5dae8e7f89e465b5b3b9c6a2ccb12 /scripts/gdb/linux/utils.py | |
| parent | Linux 6.13-rc1 (diff) | |
| download | wireguard-linux-ae6040cd7c7f8e80deefe5a49691734480f97409.tar.xz wireguard-linux-ae6040cd7c7f8e80deefe5a49691734480f97409.zip | |
clk: versaclock3: Prepare for the addition of 5L35023 device
The 5P35023 and 5L35035 Versa 3 clock generator variants are different but
the versaclock3 driver could be used with small adjustments. The features
that are implemented in driver and differs b/w variants are the PLL2 Fvco
and clock sel bit for SE2 clock. Adjust the driver to prepare for the
addition of 5L35023 device.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20241210170953.2936724-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions