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| author |   Rohit Visavalia <rohit.visavalia@amd.com> | 2025-01-06 20:40:38 -0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2025-01-07 11:48:23 -0800 |
| commit | b00b08a59674eacc77848d852d7c37de485add81 (patch) | |
| tree | 9e4269ae8526b51e2f57c0d59e18711f1ab7a65d /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: clock: xilinx: Convert VCU bindings to dtschema (diff) | |
| download | wireguard-linux-b00b08a59674eacc77848d852d7c37de485add81.tar.xz wireguard-linux-b00b08a59674eacc77848d852d7c37de485add81.zip | |
dt-bindings: clock: xilinx: Add reset GPIO for VCU
It is marked as optional as some of the ZynqMP designs are having vcu_reset
(reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
axi_gpio or PS GPIO so there will be no GPIO entry.
Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
Link: https://lore.kernel.org/r/20250107044038.100945-3-rohit.visavalia@amd.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions