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| author |   Jian Hu <jian.hu@amlogic.com> | 2024-12-31 14:25:52 +0800 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2025-03-14 16:20:23 +0100 |
| commit | b3c221e752c4e46fd86d6e15153fa8c38bc3f250 (patch) | |
| tree | 9db727caa6169d0f3deebbc0d402916ed2690625 /scripts/gdb/linux/utils.py | |
| parent | clk: amlogic: gxbb: drop non existing 32k clock parent (diff) | |
| download | wireguard-linux-b3c221e752c4e46fd86d6e15153fa8c38bc3f250.tar.xz wireguard-linux-b3c221e752c4e46fd86d6e15153fa8c38bc3f250.zip | |
clk: amlogic: a1: fix a typo
Fix a typo in MODULE_DESCRIPTION for a1 PLL driver, S4 should be A1.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Reviewed-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241231062552.2982266-1-jian.hu@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions