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| author |   Michael Turquette <mturquette@linaro.org> | 2014-11-28 21:00:16 -0800 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2014-11-28 21:00:16 -0800 |
| commit | b572b5f821abb350439609f367bd35961f53a28e (patch) | |
| tree | 380542ae6d32a0f32763062af3194d9628560123 /scripts/gdb/linux/utils.py | |
| parent | clk: clk-s2mps11: fix semicolon.cocci warnings (diff) | |
| parent | clk: rockchip: Add support for the mmc clock phases using the framework (diff) | |
| download | wireguard-linux-b572b5f821abb350439609f367bd35961f53a28e.tar.xz wireguard-linux-b572b5f821abb350439609f367bd35961f53a28e.zip | |
Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
- clock phase setting capability for the rk3288 mmc clocks
- pll init to allow syncing to actual rate table values
- some more exported clocks
- fixes for some clocks (typos etc) all of them not yet used
in actual drivers
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions