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| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-11-15 15:43:54 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-12-03 10:19:19 +0100 |
| commit | b73435047ef74c82d6e82c333810eba0038f9cf7 (patch) | |
| tree | 6759aac014dbaf950ac4670aa912bfb27e20e0f0 /scripts/gdb/linux/utils.py | |
| parent | clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSI (diff) | |
| download | wireguard-linux-b73435047ef74c82d6e82c333810eba0038f9cf7.tar.xz wireguard-linux-b73435047ef74c82d6e82c333810eba0038f9cf7.zip | |
clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs
The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug
console and is already enabled. Add clock, reset and power domain
support for the remaining ones.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241115134401.3893008-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions