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| author |   Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-02-04 07:49:49 +0900 |
|---|---|---|
| committer |   Kukjin Kim <kgene@kernel.org> | 2015-02-04 07:49:49 +0900 |
| commit | cfe3b8933cdede8bc8cc3c03931908bb17a114f4 (patch) | |
| tree | cd1afc1bd09b911557c26af1d821142272a13e65 /scripts/gdb/linux/utils.py | |
| parent | ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi (diff) | |
| download | wireguard-linux-cfe3b8933cdede8bc8cc3c03931908bb17a114f4.tar.xz wireguard-linux-cfe3b8933cdede8bc8cc3c03931908bb17a114f4.zip | |
ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2
In order to get exact 24MHz clock frequency value for the camera
sensor and avoid rounding errors the parent clock must be CLK_XUSBXTI,
not CLK_MOUT_MPLL_USER_T. Currently the sensor's master clock
frequency is too high and the sensor doesn't work properly.
This fixes commit 0357a4438d531ef3cf529e80ffcd208eb8e35f55
("ARM: dts: Specify default clocks for Exynos4 camera devices").
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions