diff options
| author |   Bjorn Helgaas <bhelgaas@google.com> | 2024-11-25 13:40:56 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-11-25 13:40:56 -0600 |
| commit | 0683141812ce93a6604c51b60101744577c65154 (patch) | |
| tree | 98c28144ea7edd80ccfe7a57b37d69ba21de559c /scripts/generate_rust_analyzer.py | |
| parent | Merge branch 'pci/virtualization' (diff) | |
| parent | dt-bindings: PCI: snps,dw-pcie: Drop "#interrupt-cells" from example (diff) | |
| download | wireguard-linux-0683141812ce93a6604c51b60101744577c65154.tar.xz wireguard-linux-0683141812ce93a6604c51b60101744577c65154.zip | |
Merge branch 'pci/dt-bindings'
- Update mediatek-gen3 DT binding to require the exact number of clocks for
each SoC (Fei Shao)
- Add qcom SAR2130P DT binding with an additional clock (Dmitry Baryshkov)
* pci/dt-bindings:
dt-bindings: PCI: snps,dw-pcie: Drop "#interrupt-cells" from example
dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible
dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions