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author | 2023-06-06 07:54:01 -0700 | |
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committer | 2023-06-06 15:59:16 +0100 | |
commit | 0760d5d0e9f0c0e2200a0323a61d1995bb745dee (patch) | |
tree | b2c71746db527e0b977da8519bdd7c4e38cefa03 /scripts/generate_rust_analyzer.py | |
parent | spi: spl022: Probe defer is no error (diff) | |
download | wireguard-linux-0760d5d0e9f0c0e2200a0323a61d1995bb745dee.tar.xz wireguard-linux-0760d5d0e9f0c0e2200a0323a61d1995bb745dee.zip |
spi: dw: Add compatible for Intel Mount Evans SoC
The Intel Mount Evans SoC's Integrated Management Complex uses the SPI
controller for access to a NOR SPI FLASH. However, the SoC doesn't
provide a mechanism to override the native chip select signal.
This driver doesn't use DMA for memory operations when a chip select
override is not provided due to the native chip select timing behavior.
As a result no DMA configuration is done for the controller and this
configuration is not tested.
The controller also has an errata where a full TX FIFO can result in
data corruption. The suggested workaround is to never completely fill
the FIFO. The TX FIFO has a size of 32 so the fifo_len is set to 31.
Signed-off-by: Abe Kohandel <abe.kohandel@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20230606145402.474866-2-abe.kohandel@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
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