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| author |   Niravkumar L Rabara <niravkumar.l.rabara@intel.com> | 2024-12-04 14:33:38 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2024-12-09 13:06:24 +0000 |
| commit | 25fb0e77b90e290a1ca30900d54c6a495eea65e2 (patch) | |
| tree | 1fe74179c9ecea3705c56caf2ead30565c996b3e /scripts/generate_rust_analyzer.py | |
| parent | spi: rockchip: Fix PM runtime count on no-op cs (diff) | |
| download | wireguard-linux-25fb0e77b90e290a1ca30900d54c6a495eea65e2.tar.xz wireguard-linux-25fb0e77b90e290a1ca30900d54c6a495eea65e2.zip | |
spi: spi-cadence-qspi: Disable STIG mode for Altera SoCFPGA.
STIG mode is enabled by default for less than 8 bytes data read/write.
STIG mode doesn't work with Altera SocFPGA platform due hardware
limitation.
Add a quirks to disable STIG mode for Altera SoCFPGA platform.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Link: https://patch.msgid.link/20241204063338.296959-1-niravkumar.l.rabara@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions