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| author |   Paolo Bonzini <pbonzini@redhat.com> | 2024-12-13 13:59:20 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-12-13 13:59:20 -0500 |
| commit | 3522c419758ee8dca5a0e8753ee0070a22157bc1 (patch) | |
| tree | 92ee4fcefeb5e39dd3c4410c3fe618c890e565e8 /scripts/generate_rust_analyzer.py | |
| parent | KVM: x86: Cache CPUID.0xD XSTATE offsets+sizes during module init (diff) | |
| parent | RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit (diff) | |
| download | wireguard-linux-3522c419758ee8dca5a0e8753ee0070a22157bc1.tar.xz wireguard-linux-3522c419758ee8dca5a0e8753ee0070a22157bc1.zip | |
Merge tag 'kvm-riscv-fixes-6.13-1' of https://github.com/kvm-riscv/linux into HEAD
KVM/riscv fixes for 6.13, take #1
- Replace csr_write() with csr_set() for HVIEN PMU overflow bit
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions