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| author |   Conor Dooley <conor.dooley@microchip.com> | 2024-08-06 18:36:21 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2024-10-24 16:27:10 +0100 |
| commit | 384f2024e1a100b9b977a697f5e7cb151b00550d (patch) | |
| tree | 5cfb7866e96518d5455c69db0aa8303f0c6cbac5 /scripts/generate_rust_analyzer.py | |
| parent | riscv: dts: starfive: Update ethernet phy0 delay parameter values for Star64 (diff) | |
| download | wireguard-linux-384f2024e1a100b9b977a697f5e7cb151b00550d.tar.xz wireguard-linux-384f2024e1a100b9b977a697f5e7cb151b00550d.zip | |
MAINTAINERS: invert Misc RISC-V SoC Support's pattern
There are now more directories that someone else maintains than ones I
do, so invert the pattern to cover included, rather than included
directories. Ditto for the bindings directory - there's more files there
that are the responsibility of others than mine (and I get CCed on all
bindings anyway). Remove it from the entry.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions