diff options
| author |   Dylan Jhong <dylan@andestech.com> | 2023-03-10 15:50:21 +0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-14 19:15:34 -0700 |
| commit | 47dd902aaee9b9341808a3a994793199e7eddb88 (patch) | |
| tree | 643810c7d2804b9b0dedee8d51f25c1cf3ea024d /scripts/generate_rust_analyzer.py | |
| parent | Merge patch series "riscv: asid: switch to alternative way to fix stale TLB entries" (diff) | |
| download | wireguard-linux-47dd902aaee9b9341808a3a994793199e7eddb88.tar.xz wireguard-linux-47dd902aaee9b9341808a3a994793199e7eddb88.zip | |
RISC-V: mm: Support huge page in vmalloc_fault()
Since RISC-V supports ioremap() with huge page (pud/pmd) mapping,
However, vmalloc_fault() assumes that the vmalloc range is limited
to pte mappings. To complete the vmalloc_fault() function by adding
huge page support.
Fixes: 310f541a027b ("riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT")
Cc: stable@vger.kernel.org
Signed-off-by: Dylan Jhong <dylan@andestech.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20230310075021.3919290-1-dylan@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions