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| author |   Jacky Bai <ping.bai@nxp.com> | 2023-03-31 14:38:12 +0800 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@linaro.org> | 2023-04-09 17:12:49 +0300 |
| commit | 4883200d8c0b20cc3bf90fcd3b837a344a31ac66 (patch) | |
| tree | 49e3bc85c6d15b7c75f38a4dcc18c430bdf8e49f /scripts/generate_rust_analyzer.py | |
| parent | clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate (diff) | |
| download | wireguard-linux-4883200d8c0b20cc3bf90fcd3b837a344a31ac66.tar.xz wireguard-linux-4883200d8c0b20cc3bf90fcd3b837a344a31ac66.zip | |
clk: imx: imx8ulp: keep MU0_B clock enabled always
Keep the A35<->M33 MU0_B clock enabled always for low power
communication.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230331063814.2462059-4-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions