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| author |   Purushothama Siddaiah <psiddaiah@mvista.com> | 2024-12-05 12:34:26 +0530 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2024-12-05 11:32:26 +0000 |
| commit | 4c6ac5446d060f0bf435ccc8bc3aa7b7b5f718ad (patch) | |
| tree | 1a55bfa84ca86c358b3cec45b4e4c29b84fac00c /scripts/generate_rust_analyzer.py | |
| parent | spi: intel: Add Panther Lake SPI controller support (diff) | |
| download | wireguard-linux-4c6ac5446d060f0bf435ccc8bc3aa7b7b5f718ad.tar.xz wireguard-linux-4c6ac5446d060f0bf435ccc8bc3aa7b7b5f718ad.zip | |
spi: omap2-mcspi: Fix the IS_ERR() bug for devm_clk_get_optional_enabled()
The devm_clk_get_optional_enabled() function returns error
pointers(PTR_ERR()). So use IS_ERR() to check it.
Verified on K3-J7200 EVM board, without clock node mentioned
in the device tree.
Signed-off-by: Purushothama Siddaiah <psiddaiah@mvista.com>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Link: https://patch.msgid.link/20241205070426.1861048-1-psiddaiah@mvista.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions