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| author |   Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> | 2023-03-27 11:56:37 +0530 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2023-03-27 12:08:51 -0700 |
| commit | 595c88cda65d30c6b36277c232193295a45406dc (patch) | |
| tree | d78f8744e03d5cb458670e6697f3de27fcd64e8c /scripts/generate_rust_analyzer.py | |
| parent | clk: zynqmp: pll: Remove the limit (diff) | |
| download | wireguard-linux-595c88cda65d30c6b36277c232193295a45406dc.tar.xz wireguard-linux-595c88cda65d30c6b36277c232193295a45406dc.zip | |
clocking-wizard: Support higher frequency accuracy
Change the multipliers and divisors to support a higher
frequency accuracy if there is only one output.
Currently only O is changed now we are changing M, D and O.
For multiple output case the earlier behavior is retained.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20230327062637.22237-1-shubhrajyoti.datta@amd.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions