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| author |   Stephen Boyd <sboyd@kernel.org> | 2025-05-17 20:46:38 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-05-17 20:46:38 -0700 |
| commit | 6a56880562d470b7bbdd1d955ff3fad4ad73a74f (patch) | |
| tree | 62a996cec3206445cfb205156b64f25f25f0fc65 /scripts/generate_rust_analyzer.py | |
| parent | clk: s2mps11: initialise clk_hw_onecell_data::num before accessing ::hws[] in probe() (diff) | |
| parent | clk: sunxi-ng: d1: Add missing divider for MMC mod clocks (diff) | |
| download | wireguard-linux-6a56880562d470b7bbdd1d955ff3fad4ad73a74f.tar.xz wireguard-linux-6a56880562d470b7bbdd1d955ff3fad4ad73a74f.zip | |
Merge tag 'sunxi-clk-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull Allwinner clk driver fixes from Chen-Yu Tsai:
Only two changes:
- Fix the order of arguments in clk macro for
SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT that was recently introduced in
v6.15-rc1
- Add missing post-divider for D1 MMC clocks to correct halved
performance
* tag 'sunxi-clk-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: d1: Add missing divider for MMC mod clocks
clk: sunxi-ng: fix order of arguments in clock macro
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions