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| author |   Xiao Yang <yangx.jy@fujitsu.com> | 2023-07-20 00:31:03 +0800 |
|---|---|---|
| committer |   Vishal Verma <vishal.l.verma@intel.com> | 2023-07-20 23:35:22 -0600 |
| commit | 70d49bbf962ce4579bebd82938ef7f265bc3e6ae (patch) | |
| tree | 83895e6f60745e91207773b9382671571ec31df8 /scripts/generate_rust_analyzer.py | |
| parent | cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws() (diff) | |
| download | wireguard-linux-70d49bbf962ce4579bebd82938ef7f265bc3e6ae.tar.xz wireguard-linux-70d49bbf962ce4579bebd82938ef7f265bc3e6ae.zip | |
tools/testing/cxl: Remove unused SZ_512G macro
SZ_512G macro has become useless since commit b2f3b74e1072
("tools/testing/cxl: Move cxl_test resources to the top of memory")
so remove it directly.
Signed-off-by: Xiao Yang <yangx.jy@fujitsu.com>
Link: https://lore.kernel.org/r/20230719163103.3392-1-yangx.jy@fujitsu.com
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions